The present invention relates to semiconductor devices and methods of fabricating the same, more particularly, to device isolation structures of semiconductor devices and methods of fabricating the same.
A typical semiconductor integrated circuit device has various components arranged in and/or on a substrate. The components are electrically connected in accordance to perform specific functions. The components are generally electrically isolated except for certain electrical connections. Device isolation structures are used to provide electric isolation between neighboring components.
As the level of integration of semiconductor devices has increased, the size of device isolation structures has decreased. In order to address this situation, a variety of new device isolation structures have been developed.
Semiconductor devices commonly include regions of varying circuit density. For example, a cell array region of a memory device may have a relatively high pattern density, while a peripheral circuit region of the memory device may have a relatively low pattern density. The peripheral circuit region may have portions with a relatively high operational voltage and portions with a relatively low operational voltage. It is generally desirable that a device isolation structure in the region with a high operation voltage has a high electric isolation ability. Accordingly, a depth of a device isolation structure in the high voltage region is commonly deeper than a device isolation structure in the low voltage region. Commonly, trench isolation is used in high voltage regions.
FIGS. 1 and 2 are cross-sectional views illustrating a device isolation structure of a conventional semiconductor device. The memory device illustrated in FIG. 1 has a cell region with a high pattern density. The high pattern density region includes a low voltage region with a low driving voltage and a high voltage region with a high driving voltage. A device isolation structure includes a cell trench isolation layer 22a formed in a cell region of a substrate 10, a low voltage trench isolation layer 22b formed in a low voltage portion of a peripheral region, and first and second high voltage trench isolation layers 22c and 22d formed in respective trenches 18 and 16 in a high voltage portion of a peripheral region. An insulation layer is also disposed in a cell trench 12 and a low voltage trench 14.
As a high operational voltage is applied in the high voltage region, it is preferable that trench isolation regions therein be relatively deep. However, the cell region and the low voltage region may have relatively high pattern density in comparison with the high voltage region. Thus, the aspect ratio of trenches in these regions may be high in comparison to those in the high voltage region. Accordingly, the trenches in the cell region and the low voltage region may not sufficiently fill with insulating material, and may therefore form voids 30.